Phase synchronization circuits that output an oscillation signal whose phase is synchronized with an input signal (also called “PLLs”, or “phase locked loops”, hereinafter) have for some time been widely used in applications such as suppressing jitter in input signals of communication apparatuses and the like, clock frequency crossover, and so on. Phase synchronization circuits are also applied in apparatuses that measure biological information, such as heart rate, pulse rate, or the like (see Patent Document 1, for example). A light-receiving device described in Patent Document 1 converts a pulse wave signal contained in an optical signal detected by a light-receiving element into a digital signal using a hysteresis comparator, and measures a pulse beat interval by measuring an interval of pulses in the digital signal with a timer that uses a phase synchronization circuit.
With a phase synchronization circuit, it is preferable that the cutoff frequency of a loop filter be set while taking jitter, noise, and so on contained in the input signal into consideration so as to stabilize the output of the oscillation signal. Here, Patent Document 2 discloses a phase synchronization circuit that appropriately changes the cutoff frequency of a loop filter in accordance with jitter in an input signal. Specifically, in addition to a first phase synchronization circuit including a first phase comparator, a first loop filter, and a first oscillation circuit, this phase synchronization circuit further includes a PLL circuit that generates a reference signal whose phase is synchronized with the input signal and that has less phase noise than the input signal, a second phase comparator that detects a phase difference between the input signal and the reference signal, a low pass filter that integrates that output, and a filter control unit that controls the cutoff frequency of the first loop filter on the basis of a frequency component obtained by analyzing the frequency of that output. The cutoff frequency of the first loop filter is changed as appropriate in accordance with jitter in the input signal.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2007-105133.
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2007-251571.
Incidentally, because pulse rates vary over time, biological signals such as electrocardiographs, photoplethysmographs, and so on experience a wider range of frequency fluctuation than the jitter in an input signal of a communication apparatus or the like, and are also more susceptible to artifacts (noise) superimposed on the signal due to body movements or the like.
Here, in the case where the phase synchronization circuit disclosed in Patent Document 2 is applied in an apparatus that measures biological information, an output signal that is less affected by jitter can be obtained by comparing the phases of the output of the PLL circuit, which has little phase noise, with the input signal (biological signal) in order to extract only a jitter component, and then controlling the cutoff frequency of the loop filter in accordance with the amount of jitter. However, according to this phase synchronization circuit, fluctuations in the output of the phase comparator caused by fluctuations in the base frequency of the biological signal cannot be distinguished from fluctuations in the output of the phase comparator caused by fluctuations in artifacts such as jitter. Therefore, even if there is no jitter in the biological signal, when the base frequency of the biological signal fluctuates suddenly, the cutoff frequency of the loop filter is controlled in the same manner as if there was superimposed jitter, which can greatly worsen the lock-up time of the PLL.